module counter 
#(
	parameter cnt_max = 25'd24_999_999
)
	(   
	
    input wire clk,
    input wire rst_n,

    output reg led_out
);

reg [24:0] cnt;

always @(posedge clk or negedge rst_n)
    if(!rst_n )
        cnt <= 25'd0;
    else if(cnt == cnt_max)
        cnt <= 25'd0;
    else
        cnt <= cnt+25'd1;



endmodule